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Publication Number: FHWA-HRT-12-072
Date: May 2013

 

Smart Pavement Monitoring System

CHAPTER 2. SMART SENSING SYSTEM DEVELOPMENT

This chapter describes the electronics design for the fatigue sensor as well as the manufacturing and testing of the small scale electronics in a standard 0.02-mil (0.5-μm) CMOS process. The self-powered FG array sub-system sensor is capable of computing and storing the applied cumulative strain history. The manufactured prototypes show robustness with respect to temperature variations and manufacturing mismatches.

2.1 SELF-POWERED SENSOR DESIGN

A complete circuit implementation of the developed system is shown in figure 2. It consists of a cascaded current reference, a startup circuit, and an array of seven injector channels. Each channel consists of an FG injector (F1–F7) whose source is connected to the current reference through multiple diode-connected P-type metal oxide semiconductor (PMOS) transistors. For purposes of clarity, the tunneling node for each injector is not shown in the schematic. Transistors M1–M8 and resistor R form a standard current reference circuit biased in the weak-inversion region, which produces a constant current reference. The reference current is copied by mirrors P1–P14, which provide source currents to all seven injector channels. A detailed description of the sensor's functionalities and the measured results are presented in figure 2.

This figure shows a complete circuit implementation of a self-powered event counter. It consists of a cascaded current reference, a startup circuit, and an array of seven injectors labeled F1-F7. One injector channel consists of two p-type metal oxide semiconductors (PMOS) in cascode (P1-P14), a diode chain (D1-D6), a floating gate PMOS, and the control capacitor (C1-C7). In the first channel, there is no diode chain, and in the second, there is one PMOS within the diode chain and one PMOS increment for each subsequent channel. The part of the circuit labeled  Reference  contains four PMOS (M1, M2, M5, and M6), four N-type metal oxide semiconductors (M3, M4, M7, and M8), and a resistor, R.
Figure 2. Illustration. Complete circuit implementation of the self-powered event counter.

 

An FG transistor is a metal oxide semiconductor field effect transistor (MOSFET) whose polysilicon gate is completely surrounded by an insulator, which in a standard CMOS fabrication process is silicon dioxide (SiO2). Because the gate is surrounded by high-quality insulation, any electrical charges injected onto this gate are retained for a long time (greater than 8 years). This makes FG transistors attractive for designing non-volatile memories. A P-channel FG MOSFET was used instead of its N-channel counterpart due to limitations imposed by the 0.02-mil (0.5-μm) CMOS process that was chosen for fabrication. Figure 3 shows a cross section of a P-channel FG metal oxide semiconductor transistor, which is used to illustrate the mechanism of impact-ionized hot electron injection (IIHEI). IIHEI in the PMOS transistor occurs when a high electric field is formed at the drain-to-channel depletion region. Due to this high electric field, the holes, which are the primary carriers in PMOS transistors, gain significant energy to dislodge electrons by impact ionization (see figure 3). The released hot electrons accelerate toward the channel region and gain kinetic energy in the process. When the kinetic energy exceeds the Si-SiO2 (> 3.2 eV) barrier and if the momentum vector is correctly oriented toward the Si-SiO2 barrier, the electrons are successfully injected into the oxide. The injection process is also shown using an energy band diagram in figure 4. As electrons are injected into the oxide and the FG, its potential decreases. One of the disadvantages of using IIHEI as a computational medium is that it requires a large voltage for operation. For example, in a 0.02-mil (0.5-μm) CMOS process, a drain-to-source voltage greater than 4.1 V is required to start IIHEI in a PMOS transistor. Fortunately, commonly available piezoelectric materials are capable of generating large voltages (> 10 V) although with limited current driving capability (< 1μA). The limited current driving capability is not a problem for IIHEI since it has been shown that when the PMOS transistor is biased in weak inversion, the injection efficiency (ratio of injection current and source/drain current) is practically constant for different values of source current. The principle of operation of the piezo-driven usage monitor is shown in figure 5 where a piezoelectric sensor converts mechanical energy into electrical energy, which is then used to inject electrons on the FG. The total number of electrons on the FG is therefore indicative of the count of mechanical events. However, IIHEI is a positive feedback process. As more electrons are injected into the FG, its potential decreases, which in turn increases the drain current through the PMOS transistor. An increase in the drain current increases the probability of impact ionization, thus increasing the hot electron injection current. If left uncontrolled, IIHEI leads to the breakdown of the transistor. Therefore, the current through the transistor is required to be carefully controlled in order to perform any useful and long-term computation.

This figure shows a cross sectional view of an impact-ionized hot electron injection (IIHEI) process in a p-type metal oxide semiconductor (PMOS) floating gate (FG) transistor. The source is on the left, and the drain is on the right. There is an insulator surrounding both the drain and source, and it runs between the two with the gate positioned above it. There is a hole at the source, and an electron is traveling through the insulator from the source to the drain and then escaping from the top through the gate. Depletion is accumulating in the insulation below the drain. The entire system is surrounded by an n-well.
Figure 3. Illustration. IIHEI process in a PMOS FG transistor.

 

This figure shows an impact-ionized hot electron injection (IIHEI) using an energy band diagram. The insulator (silica dioxide) is in the shape of a trapezoid and is positioned sideways. The gate is on the bottom left of the insulator while the drain is on the bottom right. The horizontal bottom length is shown to be tox. On the drain side, there are two half arcs that extend from the insulator. The top is labeled E subscript o, and the bottom is labeled E subscript v. Two hot electrons are just above E subscript o, and there is an arrow extending to the top corner of the insulator (closest to the drain). The distance from the position where the arch begins on the insulator to the top is labeled 3.2 eV.
Figure 4. Illustration. IIHEI using an energy band diagram.

 

This figure shows an illustration of the piezoelectricity-driven impact-ionized hot electron injection (IIHEI). The circuit begins with a connector attached to a capacitor that is connected in series to a p-type metal oxide semiconductor, which is then connected to a circuit parallel to a piezoelectric transducer. The current travels counterclockwise around the circuit.
Figure 5. Illustration. Concept of piezoelectricity-driven IIHEI.

 

A circuit model of a current-starved FG injector is shown in figure 6. It consists of a PMOS FG transistor whose drain is connected to a constant source current. Note that the FG node, Vfg, is insulated by the transistor gate oxide and other coupling capacitors. The choice of using a PMOS FG transistor (as opposed to an N-type metal oxide semiconductor (NMOS) transistor) was to ensure compatibility with the CMOS n-well (i.e., name of base layer) fabrication process used for prototyping.

This figure shows an electrical model of an analog floating gate (FG) cell. The circuit begins with V subscript piezo (+) connected to a current source labeled I subscript s. This leads to a node that splits into two. The right half goes to current source I subscript d, which is parallel to a resistor labeled r subscript o, and they are connected to a node labeled V subscript piezo (-). From where the circuit splits going to the left side, there is a circuit containing a current source labeled I subscript inj and a parallel capacitor labeled C subscript gs. Between them is a node where the wire splits into three, with one of the other wires going to capacitor C subscript fg and connector V subscript cg and the other to capacitor C subscript tun and connector V subscript tun.
Figure 6. Illustration. Electrical model of an analog FG memory cell.

 

The current source in figure 6 is powered using a potential source, V, which for the sake of this derivation is assumed to be generated from the transducer signal. Figure 6 also shows a tunneling node, Vtun, which is used for removing electrons from the gate and for initializing the FG node, Vfg. The FG voltage is also modulated using the control gate terminal, Vcg. For the analysis presented in this section, both Vcg and Vtun are assumed to be constant, and the source voltage, Vs, has been properly initialized (using tunneling or the IIHEI) to be a predetermined value. Under these conditions, the source current drives the source node to a higher voltage, which then creates a sufficient electric field at the drain-to-channel region, triggering onset of the IIHEI process. As hot electrons are injected onto the floating node, the potential Vfg decreases, resulting in a decrease in Vs. The process stops only when the source-to-gate voltage is large enough that the transistor source current equals the constant current source. To understand the dynamics of this simplified circuit, an empirical model for IIHEI is first integrated with transistor characteristics. Although several empirical formulations exist for modeling the process of IIHEI, the following expression in figure 7 for the injection current is found to be sufficient to characterize the dynamics of the injector.

I subscript inj equals beta times I subscript s times e raised to the power of V subscript sd divided by V subscript inj.
Figure 7. Equation. IIHEI current.

 

Where:
β and Vinj = Functions of transistor size and process parameters.
Is = Source current.
Vsd = Source-to-drain voltage.

By controlling the constant current source (also the source current) in figure 6, the FG transistor can be biased in the weak inversion regime. The reason for biasing the transistor in weak inversion is to reduce the power dissipation and obtain a log-linear response (shown in this derivation). In weak inversion, the source current, Is, through the transistor, Mp, can also be expressed as shown in figure 8.

I subscript s equals I subscript 0 times e raised to power of -k times the fraction V subscript fg divided by U subscript T times e raised to the power of the fraction V subscript s divided by U subscript T.
Figure 8. Equation. Source current.

 

Where:
I0 = Pre-exponential component.
Vfg = FG voltage.
Vs = Source voltage.
κ = FG efficiency.
UT = Thermal voltage (26 mV at 300 K).

For the constant source current Is, the relationship between the source voltage and the FG voltage can be obtained from figure 9.

V subscript fg equals V subscript s divided by k minus U subscript T divided by k times the natural log of open parenthesis I subscript S divided by I subscript 0 closed parenthesis.
Figure 9. Equation. FG voltage.

 

Applying figure 9 into figure 7 and expressing the injection current as the change of the FG voltage with respective to time, the equation in figure 10 was created.

I subscript inj equals negative C subscript t times the derivate of V subscript fg divided by the derivate of t equals negative C subscript t times the derivate of open bracket V subscript s divided by k minus U subscript T divided by k times the natural log of open parenthesis I subscript s divided by I subscript 0 closed parenthesis closed bracket divided by the derivative of t equals beta times I subscript s times e raised to the power of V subscript s divided by V subscript inj.
Figure 10. Equation. Injection current as a function of the FG voltage.

 

Where:
Ct = Total capacitance of the floating node Vfg.

From figure 10, the differential equation for Vs can be expressed using figure 11 and figure 12.

The derivative of V subscript s divided by the derivative of t equals  negative K subscript 1 times e raised to the power of k subscript 2 times V subscript s.
Equation 11. Equation. Differential equation for the source voltage.

 

K subscript 1 equals k times beta times I subscript s divided by C subscript t and K subscript 2 equals 1 divided by V subscript inj.
Equation 12. Equation. System variables.

 

Where:
K1 and K2 = Constants.

The general solution of figure 11 can be expressed using the equation in figure 13.

V subscript s times open parenthesis t closed parenthesis equals the negative of 1 divided by K subscript 2 times the natural log of open parenthesis K subscript 1 times K subscript 2 times t plus e raised to the power of negative K subscript 2 times V subscript s0 closed parenthesis.
Figure 13. Equation. Source voltage as a function of the cumulative duration of the injection process, t.

 

Where:
Vs0 = Initial source voltage.
 t = Cumulative duration of the injection process.

2.2 PRELIMINARY LABORATORY EVALUATION

The self-powered sensor design (described in section 2.1) was submitted and manufactured in a standard 0.02-mil (0.5-μm) CMOS process. Figure 14 shows a prototype chip on a dual in-line package (DIP)40. The actual electronics are included on 0.0015-inch2 (0.9678-mm2) area with silicon at the center. The selected packaging is suitable for laboratory testing and can be easily integrated on a testing board as shown in figure 15. The board was designed and interfaced with a computer. Data are uploaded from the sensor to the database using a MATLAB® program. The wireless interface, designed and integrated on a chip, alleviates the need for a test board. Data can be uploaded directly using a wireless protocol. The test board was used throughout the project as an easy way to manipulate testing support for the developed prototypes. These tests allow for the identification of possible manufacturing mismatches and the verification of all expected basic functionalities of the circuits.

This figure shows a sensor prototype manufactured on a dual-in-line package (DIP)40. The DIP40 packaging system is a blue rectangle, and the chip is a white square and is centered in the middle. The sensor electronics are in the center of the chip.
Figure 14. Photo. Sensor prototype manufactured on a DIP40 packaging system.

 

This figure shows the testing board that the sensor prototype is mounted to. The testing board is square, and the prototype is mounted near the center. There are several wires running throughout the board, and a wire extends from the board and is connected to the computer for data upload.
Figure 15. Photo. Prototype mounted on a testing board and connected to a computer using a parallel port for data upload.

 

Figure 16 shows the source voltage variation with respect to the injection duration as predicted by figure 13 and also according to the measured results obtained from a fabricated prototype (plotted using log and linear scale). The measured response matches the theoretical model. In particular, the response in figure 16 shows two interesting regions of operation. The first region, called "linear region," is observed under the condition of formula, of which figure 13 can be simplified, as shown in figure 17.

This graph shows the theoretical and measured results for source voltage response. The x-axis shows time in seconds, and the y-axis shows output voltage in volts. There is a graph inside a graph. The inner graph describes the measured results. It begins in the upper left corner at 4.55 V, decreases linearly until 4.45 V, and then further decreases until it reaches 4.3 V at 12×104 s. The outer graph shows both the measured and modeled results. They are depicted as a line and circled points, respectively. Both the modeled and measured results begin at 4.55 V and remain there until just past 103 s, where they decrease until they reach 104 s and then decrease log-linearly to 4.3 V. The constants for the model are K subscript 1 equals 0.202 times 10-22 and K subscript 2 equals 8.873.
Figure 16. Graph. Theoretical and measured results for source voltage response.

 

V subscript s times open parenthesis t closed parenthesis equals V subscript s0 minus K subscript 1 divided by K subscript 2 times e raised to the power of parenthesis K subscript 2 times V subscript s0 times t.
Figure 17. Equation. Source voltage for short-term monitoring.

 

Where the approximation ln(1 + x) ≈ x. Figure 17 demonstrates a linear response of the source voltage with respect to the injection duration (see figure 16 inset) and is useful for monitoring short-term events (typically less than a cumulative event duration of 100 s). However, for long-term monitoring, the second region of operation called the "log-linear" region is important and is observed under the condition formula. For log-linear conditions, figure 13 can be simplified to figure 18.

V subscript s times open parenthesis t closed parenthesis equals the negative value of 1 divided by K subscript 2 times the natural log of open parenthesis K subscript 1 times K subscript 2 closed parenthesis minus 1 divided by K subscript 2 times the natural log of open parenthesis t closed parenthesis.
Figure 18. Equation. Source voltage for long-term monitoring.

 

Thus, the source voltage is a logarithmic function of injection duration. The response is illustrated in figure 16 using both measured and empirical models where it is shown to be valid for time (t > 1,000 s), and it is the fundamental behavior used for designing event monitoring processors in this research. In fact, the log-linear model is valid beyond 100,000 s, where the injection currents become as small as a single electron per second. This can be readily verified from the measured response in figure 16, where the FG capacitance is 50 fF and the change in voltage observed is 20 mV over duration of 10,000 s. Another interesting result that can be seen from figure 18 is that Vs is independent of its initial value and is only dependent on the two constants, K1 and K2. The slope of the log-linear response is completely determined by 1/K2, while K1 only introduces an offset capturing artifacts arising due to biasing condition, ambient temperature, and CMOS process parameters. Thus, figure 18 also provides a model for compensating these systematic errors using a simple differential offset cancellation technique. Figure 18 can be written in its differential form as figure 19.

Delta times V subscript s times open parenthesis delta times t closed parenthesis equals 1 divided by K subscript 2 times the natural log of open parenthesis t subscript 0 divided by t subscript 0 plus delta times t closed parenthesis.
Figure 19. Equation. Change in source voltage.

 

Where t0 denotes a reference time with respect to which the differential time interval Δt is measured.

From figure 19, it is apparent that the differential operation is independent of the parameter K1. Thus, the robustness of sensor performance is directly related to K2. Several experiments were conducted to quantify the robustness of the parameter K2 to different environmental and manufacturing mismatch conditions. Figure 20 shows the responses obtained from multiple memory cells on the same sensor that were biased with different current sources (Is). The mismatch in the parameter (K2) was calculated to be less than 10 percent for a bias current variation greater than 100 percent. The result is encouraging since it implies that the precision of the current source is not critical for the operation of the FG injector.

This graph shows the injector response measured at various source currents. The x-axis shows time in seconds, and the y-axis shows the output voltage in volts. There are four lines that all start at 4.55 V. Each runs horizontally until roughly 103 s and then begins to decrease. The highest line represents when the source (I subscript s) is 8 nA and the slope of the output voltage curve (K subscript 2) is 9.2166. The second highest line represents when I subscript s is 10 nA and K subscript 2 is 8.787. The next line represents when I subscript s equals 13 nA and K subscript 2 is 10.142. The lowest line represents when I subscript s is 17 nA and K subscript 2 is 10.0604. All lines end around 4.35 V, and from the lowest line to the highest line, the times range from 3 times 10 raised to the power of 4 to 8 times 10 raised to the power of 4 s.
Figure 20. Graph. Injector response measured at various source currents.

 

Figure 21 shows the responses obtained from eight cells, three of which were measured from different prototypes fabricated in the same run, and five were measured using prototypes fabricated in different runs. For these measurements, the mismatch in the parameter K2 was calculated to be 4.3 percent. The results demonstrate that the response of the injector is robust to fabrication-related mismatch.

This graph shows the injector response measured by using eight prototypes fabricated in different runs. There are two graphs in the figure: a bar graph shown in the bottom left corner of a larger line graph. For the bar graph, chip number is on the x-axis ranging from 1 through 8, and K subscript 2 is on the y-axis. Chips 3 and 6 have the highest K subscript 2 values of 9. Chips 2 and 4 have the lowest K subscript 2 values of 8.5. The line graph shows time in seconds on the x-axis, and output voltage is in volts on the y-axis. There are eight lines, which start at 4.656 V, and they continue horizontally across the graph until around 150 s, where the lines begin to decrease to an output voltage of 4.3 to 4.35 V.
Figure 21. Graph. Injector response measured by using eight prototypes fabricated in different runs.

 

Figure 22 shows the response of the injector measured over a temperature range of 14 to 104 ºF (-10 to 40 ºC). Measured results show that the parameter K2 varies linearly with temperature, with the temperature coefficient measured to be 0.01V-1T-1. The parameter K2 therefore varies by 1V-1 for a temperature range of 212 ºF (100 ºC), showing that injector response is robust with respect to external temperature. The measured results summarized in figure 20 through figure 22 thus demonstrate that the sensor electronics are robust to variations in biasing and ambient conditions and that no internal electric corrections are required. The designed combination of the current reference and injection process constitute a self-correcting system that cancels all external artifacts due to external environmental variations and internal manufacturing mismatches.

This graph shows the injector response measured under different temperature conditions. There are two graphs in the figure: a larger line graph and a smaller graph in the bottom left corner. For the line graph, the x-axis shows time in seconds, and the y-axis shows output voltage in volts. There is a single line that extends horizontally at 4.65 V until around 100 s, when the line begins to decrease. At this point, there is an increase in temperature. The line ends at an output voltage of 4.3 V and a time slightly past 104 s. The smaller graph shows temperature in degrees Celsius on the x-axis and K subscript 2 on the y-axis. Two variables are shown on the graph: measured K subscript 2 and the model. They both increase linearly from a K subscript 2 value of 8.4 to 9 over a temperature increase of 14 to 104 °F (-10 to 40 °C). The equation for the line is given as K subscript 2 equals 0.0108 times T plus 8.52.
Figure 22. Graph. Injector response measured under different temperature conditions.

 

A manufactured sensor on a small-scale ceramic package was also manufactured and tested. The small-scale package is a ready-to-implement packaging system that was selected by the team for the latest version of the sensor. Figure 23 shows the new packaging design. Dimensions of the sensor electronics (including the computation and storage circuitry and the RF communication module) are 0.24 × 0.22 × 0.03 inches (6.09 × 5.59 × 0.76 mm). An interface board was designed and manufactured (see figure 24). It acts as an interface between the active piezoelectric element and the analog electronics. The board also contains all the electronic circuitry that interfaces the sensor with the reading antenna. The board dimensions are 0.6 × 0.6 inches (15.24 × 15.24 mm).

This photo shows a sensor connection package. There are three figures: the figure on top shows the top view, the figure on the right shows a side view, and the figure on the bottom shows a cross section area through the center of the design. The top view has dimensions of 0.23 by 0.22 inch (6.0 by 5.564 mm). The top left corner is flat and is labeled  chamfer 0.4 x 45 degrees.  The remaining corners are rounded, and the top right corner is labeled  R 0.500, 3x.  The inside length is 0.165 inch (4.240 mm). The inside of the packaging design has five notches on each side. The side view shows that the depth is 0.031 inch (0.800 mm), and the length is 0.23 inch (6.0 mm). The cross sectional area shows that there is a bottom and two sides, and the sides are slightly tapered. The inside distance at the bottom is 0.207 inch (5.310 mm), the distance from the top of the sides to the inside bottom is 0.023 inch (0.597 mm), and the distance from the top of the side to the outside bottom is 0.031 inch (0.800 mm).
Figure 23. Illustration. Sensor connection package.

 

This photo shows a sensor interface board, which contains electronic circuitry. There is a dark green square located to the left of the center with metallic lines extending from it and running to other small metallic squares all over the board.
Figure 24. Photo. Sensor interface board.

 

2.3 SENSOR ELECTRONICS REFINEMENT

During the second phase of the project, efforts focused on the following two aspects of the fatigue sensor design:

Table 1 compares the list of hardware changes that were incorporated in different versions of the sensor IC. Version 5.0 refers to the IC that was used in the FHWA field study at the ALF at TFHRC. Version 7.0 refers to the final version of the sensor IC, which incorporates all the major changes from the previous version.

Table 1. Hardware changes that were incorporated in different versions of the sensor IC.

Hardware Change Sensor Version
Version 5 Version 6 Version 7 Version 7(2)
FG array Seven-channel level detection with injection control Four-channel level and three-channel rate detection with linear injector Four-channel level and three-channel rate detection with linear injector Four-channel level and three-channel rate detection with linear injector
RF voltage rectifier Digital, analog,
and FG array
Digital, analog,
and FG array
Digital and analog Digital and analog
Ring oscillator With regulator With regulator With regulator With regulator
Analog-to-digital converter (ADC) Fully differential Single-end Single-end, feedback Single-end, feedback
Switching diode Bulk switching PMOS Bulk switching PMOS NMOS NMOS
Protection Not working No RF, piezoelectric RF, piezoelectric
Tunneling control No bulk control All bulks short to ground All bulks short to ground All bulks short to ground
Pull-down resistor 155 megaohm 188 megaohm Resistor bank Resistor bank
Channel reset No With command 01 With command 01 With command 01
Pin number 40 40 40 40
Packaging DIP40 DIP40 DIP40 Quad-flat no-leads package
Load modulation capacitor Tunable Tunable Tunable Tunable
Status Tested Tested Tested Tested

 

The important features incorporated in version 7.0 include the following:

The task of refining the sensor electronics was primarily based on debugging the prototype sensor that was extracted from the field study at TFHRC's ALF. Even though most of the individual modules on the sensor were found functional post-extraction, the testing revealed the following problems, which were addressed in the subsequent revisions of the sensor:

The approach used to address these problems included providing worst-case scenario models (e.g., the effect of reader-to-sensor distance) directly into the sensor simulation framework and then verifying if each of the modules are functional. Through this simulation study, significant changes were made to the modules, which are highlighted in red in figure 25. Each of these individual changes is summarized in the following section.

This flowchart shows the system architecture of a sensor, which includes the piezo-powered and radio frequency identification modules. The flowchart starts in the upper left hand corner begins with a coil antenna, which leads to voltage multiplier 1, voltage multiplier 2, envelope recover, and load modulation. From each of the voltage multipliers, there is a regulator. The first one leads to a power hand-off switch, which leads to a floating gate-based analog processor, a multiplexer (MUX), and then to an analog-to-digital converter. The other regulator leads to a demodulator, which is also connected to the envelope recovery. From the demodulator, there is a state-of-frame (SOF) detector and decoder, which connects to the finite state machine, followed by the 8-bit counter, and the Manchester encoder, which then leads back to the load modulation. An arrow also points from the second regulator leads to the SOF detector and decoder and also to a high voltage generator, which then leads to the floating gate-based analog processor. From the finite state machine, there are three arrows that break off: one leads to the tunneling controller and then to the high voltage generator, the second leads to an injection controller, which leads to the floating gate-based analog processor, and the third leads to a selection controller and then to the MUX.
Figure 25. Illustration. System architecture of the entire system.

2.3.1 Voltage Regulators

The first prototype version of the sensor directly used the output of the voltage multipliers to power the digital logic and the ADCs. However, experiments with fabricated prototypes have revealed that the output of the multiplier is sensitive to the coupling coefficient between the reader and sensor coil (which is a function of the distance between the two coils). As a result of this variation, the supply voltage to the digital oscillator can vary, which can change the clock frequency. Also, the output of the ADC is sensitive to the supply voltage variations. In newer versions of the sensor IC, linear regulators have been incorporated, which can clamp the output voltage irrespective of the loading current and the distance between the sensor/reader coils. Two topologies of linear regulators were used in experiments: the classic operational amplifier (OPAMP)-based regulator shown in figure 26 and a new diodic current conveyer-based regulator shown in figure 27. The response of each of the regulators is shown in figure 28 and figure 29, which plot the output voltages (one for analog supply and one for digital supply) when the distance between the sensor/reader coil is reduced. It can be seen that after a critical voltage level, the output of each of the regulators remains clamped. However, the OPAMP-based regulator has a poor power supply voltage rejection at the output due to feedback delays. Therefore, a diodic regulator was chosen in future versions of the sensor IC. The diodic regulator has additional advantages, such as having a lower voltage drop and a higher conversion efficiency.

This figure shows a conventional operational amplifier (OPAMP)-based regulator. It begins at V subscript 1 and goes to the positive input of the OPAMP. The output of the OPAMP goes to a resistor, R subscript 1. The other end of R subscript 1 ends at a node, where it splits in three. One part goes to another resistor, R subscript 2, whose other node is connected to the ground, and the second part goes to a capacitor, C, whose other plate is grounded. The third line goes to the negative input of the OPAMP.
Figure 26. Illustration. Conventional OPAMP-based regulator.

 

This figure shows a circuit that begins at a supply labeled V subscript dd, which leads to a current source labeled I subscript b, which leads to the drain of N-type metal oxide semiconductor Q1 and to the gate of Q4. The gate and drain of Q2 and Q3 are connected to the respective drains and are connected in series with Q1. The source of Q3 is grounded. The gate of Q1 and the source of Q4 are connected together and go to the capacitor C whose other plate is grounded. The drain of Q4 goes to the supply V subscript dd.
Figure 27. Illustration. Diodic current conveyer regulator.

 

This figure shows the simulated response for the operational amplifier (OPAMP)-based regulator. The x-axis shows the input voltage in volts, and the y-axis shows the output voltage in volts. There are three lines shown on the graph. The top line is red and is labeled unregulated. It begins at 2 V and increases linearly to 10 V. The second highest line is purple and is labeled analog regulator. It begins at 1.5 V and increases linearly until it reaches 4 V, where it then continues horizontally. The point where it changes from linear to a horizontal line is labeled MI(4.542V, 4.044V). The bottom line is pink and is labeled digital regulator. It begins around 0.9 V and increases linearly to 2 V, where it then continues horizontally. The point where this transition occurs is labeled MD(4.421V, 1.994V).
Figure 28. Graph. Simulated response for the OPAMP-based regulator.

 

This figure shows the simulated response for the diodic regulator. The x-axis shows the input voltage in volts, and the y-axis shows the output voltage in volts. There are three lines shown on the graph. The top line is red and is labeled unregulated. It begins at 2 V and increases linearly to 10 V. The second highest line is purple and is labeled analog regulator. It begins at 1 V and increases linearly until it reaches 4.5 V, where it then continues horizontally. The point where it changes from a linear to a horizontal line is labeled MO(6.053V, 4.61V). The bottom line is also red and is labeled digital regulator. It begins around 1 V and increases linearly until it reaches 3.4 V, where it then continues horizontally. The point where this transition occurs is labeled MI(4.709V, 3.344V).
Figure 29. Graph. Simulated response for the diodic regulator.

 

Figure 30 shows the results measured from a fabricated OPAMP-based low dropout voltage (LDO), where the supply voltage to the LDO is varied by 2 V. The output of the regular exhibits ringing, illustrating stability problems. In past studies, this condition has been alleviated through the use of compensation capacitors, which consume more power and silicon area.

The figure shows the output voltage from an operational amplifier (OPAMP)-based low dropout voltage (LDO). The x-axis shows time, and the y-axis shows voltage. Two curves are shown; both are square signals with one of the curves showing oscillations and noise in the signal, which indicates instabilities.
Figure 30. Illustration. Measured results from an OPAMP-based LDO showing potential stability problems.

 

Figure 31 and figure 32 show the measured responses from two types of diodic regulators (with different number of series diodes). Figure 31(a) shows the drop-out voltage when the input supply is increased. The output voltage remains clamped and stable when the input increases beyond a certain threshold. Figure 31(b) shows the power supply rejection ratio (PSRR) of the diodic regulator where a sinusoidal disturbance is superimposed on the supply of the regulator. The results show that the ripple at the output is significantly reduced. Similarly, figure 31(c) and figure 31(d) show line regulation and line transient experiments corresponding to the diodic regulator. Figure 32 shows similar results but for a diodic regulator with a longer chain of diodes, which generates a higher regulated output voltage.

Four graphs are showed illustrating different outputs of the regulator: the dropout voltage, the power supply rejection ratio, line regulation, and line transient.
Figure 31. Graph. Measured responses for a fabricated diodic regulator.

 

Four graphs are showed illustrating different outputs of the modified regulator with a longer diodic chain: the dropout voltage, the power supply rejection ratio, line regulation, and line transient.
Figure 32. Graph. Measured responses for a fabricated diodic regulator with a longer diodic chain.

 

Table 2 summarizes the performance metrics measured from fabricated prototypes of the diodic regulator (with different regulator configuration).

Table 2. Summary of performance metrics of fabricated prototypes.

Version Input
Range (Volts)
Output Range (Volts) Discharging
Time
PSRR at
13.56 MHz
SPS_v008 regulator 1 4.3-10 3.1-3.3 1 ms at RL = 10M
0.3 ms at RL = 1M
-24dB at RL = 10M
SPS_v008 regulator 2 5.7-10 4.2-4.5 1 ms at RL = 10M
0.3 ms at RL = 1M
-28dB at RL = 10M
RFID201107 Reg_Digital 2.7-10 1.96-2.08 2 ms at RL = 10M
0.36 ms at RL = 1M
40 ms at RL = 100K
4.2 ms at RL = 10K
-26dB at RL = 10M
-36dB at RL = 1M
-29dB at RL = 100K
-24dB at RL = 10K
RFID201111 Reg_Ana 4.8-10 3.9-4.0 0.5 ms at RL = 10M -14dB at RL = 10M
RFID201111 Reg_Dig 2.7-10 1.9-2.0 0.5 ms at RL = 10M -16dB at RL = 10M
RL = Remaining life.
M = Mega (106).
K = Kilo (103).

 

2.3.2 Additional Changes

Improvements have been made to the ADC by using large-size integrating capacitors and introducing an improved topology of a sample-and-hold circuit, which reduces the effect of channel charge injection and clock feed-through.

One of the primary sources of the data read-out problem was the substrate coupling of 13.56 MHz RF signal to the sensor and in particular to the FGs. One of the solutions to mitigate this problem is to implement an on-chip RF shield, which is difficult because current and ground loops cannot be completely avoided. Therefore, researchers decided to decouple the RF identification (RFID) module from the piezo-powered sensing module and implement the RF powering circuits on a separate silicon substrate. Figure 33 and figure 34 show the layout of two separated modules. Because they do not share a common substrate, the effect of signal coupling is significantly reduced. The RF module is responsible for generating a regulated 2 V supply voltage, which is used by the sensor module for all programming tasks. The communication interface between the two modules is a serial peripheral interface (SPI), which ensures compatibility with the previous sensor versions. An additional benefit of this decoupling is that the sensor module could be interfaced with third party RFID interrogators like an Intel® wireless identification and sensing platform, which hosts a programmable Texas Instruments (TI) MSP430TM microcontroller. This controller could be programmed to generate the SPI command and control required by the sensor module.

This figure shows the layout of a piezo-sensor module. It is shown as a purple square with several boxes outlined in white in the top right corner of the square. The box in the upper right corner is labeled charge-pump, the box to the left is labeled digital controller, the box below that is labeled bias generator, and the box next to it labeled the floating gate sensor module. Below the boxes, there is a section labeled piezo-powered sensor module.
Figure 33. Illustration. Piezo-sensor module.

 

This figure shows the radio frequency (RF) interrogation module on separate silicon substrates/integrated circuits (ICs). There is a purple square, and the top left region is labeled RF-powered sensor module. Below that, there is a box labeled tuning resistors. Below that, there are two smaller blocks; the one on the left is labeled analog-to-digital converter (ADC), and the one on the right is labeled regulators. Below those boxes, there is a box labeled digital controller. Below that, this is another box labeled modulator/demodulator, followed by a box labeled tuning resistors.
Figure 34. Illustration. RF interrogation module on separate silicon substrates/ICs.

 

2.3.3 Linear FG Sensor

The concept of the linear IIHEI device relies on maintaining the current due to an IIHEI constant. This ensures that the FG node of a PMOS transistor is discharged at a constant rate, thus implementing a non-volatile linear integrator. The hot electron injection current is typically a function of the transistor source current Is, the source-to-drain voltage, and the gate-to-drain voltage across the transistor. This dependence is highly non-linear; the exact form of this non-linear function is unknown, even though several empirical models have been reported in literature. For the proposed linear injection technique, all the factors that affect the injection current, such as the source currents and terminal voltages, are held constant so that the injection is also constant. The structure of the linear injector circuit is shown in figure 35.

This figure shows an ultra-linear floating gate (FG) injector circuit. The circuit begins at the connector labeled V subscript DD and goes to the source labeled I subscript ref. From there, it goes to a node where the circuit splits three ways. One ends at the node labeled V subscript s, the other continues to the negative input of the operational amplifier (OPAMP) labeled A, and the last one goes to the source of the p-type metal oxide semiconductor labeled M subscript fg. The drain of M subscript fg goes to the ground, and the gate goes to a node labeled V subscript fg. At that node, the circuit splits, and half goes to a capacitor labeled C subscript tun and then to a connector labeled V subscript tun, and the other half goes to a capacitor labeled C subscript fg and then to node labeled V subscript cg. At this node, the circuit splits again, and half goes to the switch S subscript 2, which is either open or grounded, the other half goes to the output of the OPAMP labeled A. V subscript ref goes to the positive input of OPAMP A. The circuits of OPAMP A and the current source I subscript ref is shown in insets.
Figure 35. Illustration. Ultra-linear FG injector circuit.

 

During the sensing mode of the injector circuit, the switch S2 is open, which activates the negative feedback loop formed by the OPAMP, A,and the FG transistor, Mfg. The source current is held constant at Iref, which ensures that the source-to-gate voltage, Vsg, remains constant during injection. OPAMP A ensures that the source-to-drain voltage Vsd is held constant. Vcg will linearly increase to maintain Vfg constant. Thus, Vgd is also held constant, and the injection current will remain constant. The programming is enabled for when the sensing signal is activated, which ensures that a fixed amount of charge is injected onto the FG. During the read-out mode, the switch S2 is closed, which makes Vcg = 0. The FG voltage Vfg of the PMOS transistor is determined by the charge injected during the sensing phase and the total capacitor at the FG node. As Iref is constant, the change in the source voltage ΔVs can be read through a unity-gain buffer as shown in figure 35.

The dynamic range of the linear FG injector circuit was measured experimentally. The supply voltage, Vdd, was set to 6.5 V, S2 was enabled, and Vs was initialized to 4.1 V (using Fowler-Nordheim tunneling).

After each sensing cycle, Vs was measured using an off-chip ADC. Figure 36 shows the measured result when Vref = 4.9 V and Iref = 50 nA and shows a close agreement with an ideal linear model. Figure 37 shows the measured resolution over a dynamic range of 4 V output. Since the least significant bit voltage for differential nonlinearity is less than 0.4 mV, the equivalent resolution is above 13.4 bits.

This figure shows measured response of the linear injector circuit showing a dynamic range greater than 4 V and resolution greater than 13 bits. Programming cycles is on the x-axis, and the measured V subscript s in volts is on the y-axis. There are two lines shown on the graph: one is a dashed line representing the ideal linear model, and the other is a solid line representing measured results. The lines are almost overlapping for the entire graph except for at the beginning and end, where close-up shots are provided. At the beginning, the measured results are on top at 4.1 V, while the ideal linear model is just below it at 4.05 V. At the end, the measured results are still on top and end at a value of 0.15 V, and the ideal linear model ends at 0.1 V.
Figure 36. Graph. Measured response of the linear injector circuit showing a dynamic range greater than 4 V and resolution greater than 13 bits.

 

This graph shows the measured resolution over a dynamic range of 4 V output. Programming cycles is on the x-axis, and least significant bit (LSB) in millivolts is on the y-axis. The graph shows that LBS ranges from 0.1 to -0.1 mV.
Figure 37. Graph. Measured resolution over a dynamic range of 4 V output.

2.3.4 Over-Voltage Protection Circuit

In the final version, a chain of protection diodes was included that clamps the voltage whenever the signal generated by the voltage multipliers or the piezoelectric transducer exceeds 10 V. Figure 38 shows the measured output from a voltage multiplier (with an overvoltage protection circuit) showing that the output remains clamped around 10 V when the input signal (i.e., the RF signal) is varied.

The figure shows the output voltage from the over protection circuit versus the input voltage. Three lines are shown for different loading times 12, 18 and 24 s. The plots show that the output remains clamped around 10 V when the input signal is varied.
Figure 38. Graph. Measured response from over-voltage protection circuit showing the output clamped to 9 V.

 

2.4 CONCLUSION

In this chapter, the basic functionalities of the electronics for signal processing and data storage of the sensor were tested, and their performances were evaluated. It was shown that the self-powered sensor is capable of continuous battery-less monitoring of strain events integrated over the occurrence duration time. The sensor is based on the integration of a piezoelectric transducer with an array of ultra-low power FG computational circuits.

 


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The Federal Highway Administration (FHWA) is a part of the U.S. Department of Transportation and is headquartered in Washington, D.C., with field offices across the United States. is a major agency of the U.S. Department of Transportation (DOT). Provide leadership and technology for the delivery of long life pavements that meet our customers needs and are safe, cost effective, and can be effectively maintained. Federal Highway Administration's (FHWA) R&T Web site portal, which provides access to or information about the Agency’s R&T program, projects, partnerships, publications, and results.
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