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Publication Number: FHWA-HRT-06-139
Date: October 2006

Traffic Detector Handbook:Third Edition—Volume II

APPENDIX H. DIGITAL PERIODSHIFT ELECTRONICS UNIT ANALYSIS

ABSTRACT

The period-shift electronics unit utilizes the change in inductance caused by a vehicle passing over a loop to measure the altered electronics unit oscillator frequency using a counter to count the number of pulses that occur during the electronics unit oscillator period.

Appendix H describes the derivation of the digital period-shift electronics unit sensitivity, which is shown to be proportional to the threshold count Npt divided by the total number of counts Npc in the frequency counter. The response time is proportional to the threshold count, divided by the product of the sensitivity and the frequency of the crystal clock.

ANALYSIS

The oscillator in a digital period-shift electronics unit operates at a frequency fD, which is determined by the loop, lead-in cable, and the electronics unit tuning network. The number m of oscillator cycles from the period scaler determines the length of the gating pulse applied to the AND gate. When the gating pulse is m times as long as the loop is occupied, more clock pulses are sent to the period counter, making the electronics unit more sensitive.

A simplified block diagram of a single channel, digital period-shift vehicle electronics unit is illustrated in Figure H-1. The change in inductance at the electronics unit terminals caused by a vehicle produces a change in the oscillator frequency. The sine wave oscillator frequency is converted by a period scaler into a square wave. The square wave is input to an AND gate, which compares the signal level (i.e., high or low) to that of the crystal clock frequency pulse.

Figure H-1 shows that the inductance at the detector terminals L sub D feeds into the detector Oscillator which in turn feeds into the detector oscillator counter. The detector oscillator counter is also adjusted by the sensitivity control. multiplier. The period counter counts the time for a fixed number of loop cycles. A comparison unit compares the time for the count with no vehicle present with the actual time. This delta difference is then compared to the threshold control and if it exceeds the threshold, a call is output.

Figure H-1. Digital period-shift electronics unit block diagram.

If both the square wave and the crystal clock pulse are high, a count is sent to the period counter. The count is equal to the number of clock pulses that occur in a period.

At the end of the period, the count is sent to the first comparator. The comparator subtracts the reference period count stored in memory, which represents the count when no vehicle is present, from the current period count. The difference enters the second comparator. If the second comparator finds that the difference is in excess of the threshold sensitivity, then a vehicle is presumed present and a call is output.

The period TDC of the electronics unit oscillator is

Equation H-1. Capital T subscript Capital D C equals the product of M times Capital T subscript Capital D. (H-1)
where
TD= 1/fD = period of electronics unit oscillator in s
fDelectronics unit oscillator frequency in Hz
mnumber of oscillator cycles from the period scaler.

The length of the gating pulse is

Equation H-2. Capital T subscript G equals the product of 0.5 times Capital T subscript capital D C which in turn equals the product of 0.5 times M times Capital T subscript Capital D. (H-2)

The number Npc of clock pulses counted by the period counter is

The count of the period counter is proportional to the electronics unit oscillator period TD

Equation H-3. Capital N subscript P C equals the Capital T subscript G divided by Capital T subscript Capital C which in turn equals 0.5 times M times Capital T subscript Capital D divided by Capital T subscript Capital C. (H-3)

where TC is the period of the crystal clock equal to the inverse of the clock frequency.

The number of clock pulses stored in the reference memory when no vehicle is present is

Equation H-4. Capital N subscript P C superscript small N V equals 0.5 times M times Capital T subscript Capital D superscript N V divided by Capital T subscript Capital C. (H-4)

The number of clock pulses counted when a vehicle is present is

Equation H-5. Capital N subscript P C superscript V equals 0.5 times M times Capital T subscript Capital D superscript V divided by Capital T subscript Capital C. (H-5)

Since the loop inductance decreases when a vehicle is sensed, the electronics unit oscillator frequency fD increases and the oscillator period TD decreases. Then

Equation H-6. F subscript Capital D superscript V is greater then F subscript Capital D superscript N V which implies that Capital N subscript C superscript N V is greater then Capital N subscript C superscript V. (H-6)

The output of the first comparator is

Equation H-7. Capital Delta Capital N subscript P lowercase C equals Capital N subscript P lowercase C superscript N V minus Capital N subscript lowercase C superscript V which in turn equals the product of parenthesis 0.5 times M divided by Capital T subscript Capital C parenthesis times parenthesis Capital T subscript Capital D superscript NV minus Capital T subscript Capital D superscript V parenthesis. (H-7)

Since

Equation H-8. Capital Delta Capital T subscript Capital D equals Capital T subscript Capital N superscript NV minus Capital T subscript Capital D superscript V. (H-8)

the output of the first comparator can be written as

Equation H-9. Capital Delta Capital N subscript P lowercase C equals the product of parenthesis 0.5 times M divided by Capital T subscript Capital C parenthesis times Capital Delta Capital T subscript Capital D. (H-9)

The output count of the first comparator is proportional to the change ΔTD in the oscillator period.

When the output count ΔNpc of the first comparator equals the threshold count Npt in the second comparator, a vehicle call results.

Then,

Equation H-10. Capital Delta Capital N subscript P C equals Capital N subscript P T. (H-10)

Thus,

Equation H-11. Capital N subscript P lowercase T equals the product of parenthesis 0.5 times M divided by Capital T subscript Capital C parenthesis times Capital Delta Capital T subscript Capital D. (H-11)

For a high quality factor tuned circuit, the normalized period shift is approximated by

Equation H-12. Capital Delta Capital T subscript Capital D divided by Capital T subscript Capital D equals 0. 5 times Capital Delta Capital L subscript Capital D divided by Capital L subscript Capital D which in turn equals 0.5 times Capital S subscript Capital D superscript P. (H-12)

Solving for sensitivity, we get

Equation H-13. Capital S subscript Capital D superscript P equals 2 times Capital Delta Capital T subscript Capital D divided by Capital T subscript Capital D. (H-13)
Equation H-14. Which in turn equals the quotient of parenthesis 4 times Capital N subscript small P lowercase T times Capital T subscript Capital C parenthesis divided by the product of m times Capital T subscript Capital D. (H-14)

Since

Equation H-15. Capital T subscript Capital C equals 1 divided by F subscript Capital C. (H-15)

and

Equation H-16. Capital T subscript Capital D equals 1 divided by F subscript Capital D. (H-16)
Equation H-17. Capital S subscript Capital D superscript P equals the quotient of parenthesis 4 times Capital N subscript P T times F subscript Capital D parenthesis divided by the product of M times f subscript Capital C. (H-17)

when

Equation H-18. F subscript Capital D equals 1 divided by parenthesis 2 times pi times the square root of parenthesis Capital L subscript Capital D times Capital C subscript Capital D parenthesis parenthesis. (H-18)
Equation H-19. Capital S subscript Capital D superscript P equals 2 times Capital N subscript P T divided by parenthesis pi times M times F subscript Capital C times the square root of parenthesis Capital L subscript Capital D times Capital C subscript Capital D parenthesis parenthesis. (H-19)

Letting

Equation H-20. Capital K subscript P equals the quotient of the product of 2 times Capital N subscript P T divided by parenthesis pi times m times F subscript Capital C parenthesis. (H-20)

the sensitivity becomes

Equation H-21. Capital S subscript Capital D superscript P equals Capital K subscript P divided by square root of parenthesis Capital L subscript Capital D times Capital C subscript Capital D parenthesis. (H-21)

since

Equation H-22. Capital N subscript P lowercase C equals 0.5 times M times Capital T subscript Capital D divided by Capital T subscript Capital C which in turn equals 0.5 times m times F subscript Capital C divided by F subscript Capital D. (H-22)

from Equation H-3,

Equation H-23. Capital S subscript Capital D superscript P equals 2 times Capital N subscript P T divided by Capital N subscript P C. (H-23)

The sensitivity of the digital period-shift electronics unit is twice the threshold count divided by the maximum number of counts on the period counter.

The response time of the digital period-shift electronics unit is primarily due to the time required to fill the period counter with clock pulses. Thus,

Equation H-24. T superscript P equals Capital N subscript P lowercase C times Capital T subscript Capital C which in turn equals Capital N subscript P lowercase C divided by F subscript Capital C. (H-24)

Rewriting equation H-23 to solve for Npc, we get

Equation H-25. Capital N subscript P C equals 2 times Capital N subscript P T divided by Capital S subscript Capital D superscript P. (H-25)

Upon substituting this result into equation H-24, the response time becomes

Equation H-26. T superscript P equals the quotient of 2 times Capital N subscript P T divided by the product of Capital S subscript Capital D superscript P times F subscript Capital C. (H-26)

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